Conventional asynchronous flow-through operations in multi-port memory devices typically include performing a write operation to a write port that is closely followed by a read operation to a read port. Such flow-through operations may include writing new data into a row of memory cells located at a first address and then allowing that newly written data to “trickle” or “fall” through the memory cells and pass out of the read port during a read operation to the same address. FIG. 1 illustrates a conventional asynchronous multi-port memory device that can perform conventional flow-through operations. This memory device includes a memory array (e.g., SRAM array) and left and write address decoders that are coupled to the memory array. Arbitration, interrupt and semaphore control logic is also provided. Left and write input/output control circuits are provided for routing input and output data between input/output lines (shown as I/O0L-17L and I/O0R-17R) and the memory array. This conventional memory device is more fully described in a product datasheet for a high-speed 4Kx18 Dual-Port Static Ram (IDT7034S/L), published by Integrated Device Technology of Santa Clara, Calif. and available at http://www.idt.com. The disclosure of this datasheet is hereby incorporated herein by reference. Conventional read, write and flow-through operations performed by asynchronous memory devices are illustrated by TABLE 1. In particular, TABLE 1 illustrates that right-to-left flow-through operations will occur when the write access to a first address by the right port precedes the read access to the same address by the left port. Likewise, left-to-right flow-through operations will occur when the write access to a first address by the left port precedes the read access to the same address by the right port.
TABLE 1Left Port (L)Right Port (R)TimingFunctionRead accessRead accessNo limitBoth read accessWrite accessWrite accessL before RR inhibitedR before LL inhibitedRead accessWrite accessL before RR inhibitedR before LR→L Flow throughWrite accessRead accessL before RL→R Flow throughR before LL inhibited
Conventional flow-through operations may also be performed by synchronous memory devices that utilize on-chip clock signals to carefully control timing of read and write operations. Such conventional flow-through operations in synchronous memory devices may be referred to as write-through-read operations. An exemplary flow-through operation is more fully described in U.S. Pat. No. 4,998,221 to Correale, Jr., entitled “Memory By-Pass for Write through Read Operations”. U.S. Pat. No. 5,699,530 to Rust et al., entitled “Circular Ram-Based First-IN/First-Out Buffer Employing Interleaved Storage Locations and Cross Pointers”, also discloses synchronous flow-through that may be utilized in a FIFO memory device. Notwithstanding these disclosures of conventional flow-through operations, there continues to be a need for asynchronous memory devices that can efficiently provide flow-through even when their memory architectures do not support conventional flow-through operations.